SOC implementation of Processor chip (Block implementation)

Tools used : Innovus, Spyglass, Conformal, CALIBRE, Star RC- XT, PrimeTime, ICV and Redhawk
Technology : 10nm

Responsibilities :
Netlist-to-GDS implementation:

  • Understanding Customer Designs, Data flow diagrams
  • Flow/tool, Library setup
  • Working with RTL Team for UPF
  • Giving constraints feedback to synthesis team for timing closure and optimization at different stages of the flow
  • Floorplaning, Power planning (Low power implementation)
  • Implementing multiple voltage Islands for multiple feedthroughs
  • Placement, Post placement timing/congestion optimization
  • CTS, Clock optimization
  • SI Aware Routing
  • Cleaning up shorts, opens and data ready for STA
  • Static Timining analysis and closure
  • ECO Implementation
  • Physical Verification
  • IR/EM Analysis
  • Final Sign off
Project Description : 3.5M instances and 304 macros 1.2 GHZ Frequency
Challenges : Understanding Eco implementation flow with short period of time and fixing DRC and LVS.

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