SOC implementation of Graphic chip (IP implementation)

Responsibilities :

• Handled Multi-Voltage IP of 14 Blocks
• Netlist-to-GDS implementation:
• Understanding Customer Designs, Data flow diagrams
• Flow/tool, Library setup
• Working with RTL Team for UPF
• Giving constraints feedback to synthesis team for timing closure and optimization at different stages of the flow

• Floorplaning, Power planning (Low power implementation)
• Implementing multiple voltage Islands for multiple feedthroughs
• Placement, Post placement timing/congestion optimization
• CTS, Clock optimization
• SI Aware Routing
• Cleaning up shorts, opens and data ready for STA
• Static Timining analysis and closure
• ECO Implementation
• Physical Verification
• IR/EM Analysis
• Final Sign off
• Writing scripts to automate the recurring tasks/steps