Physical Design And Verification

Physical Design And Verification
  • Setting up Physical Design and Verification flow/metholodology
  • Fullchip and Block level Implementation from
  • Advance Low Power methodology Implementation
  • High Speed design Implementation (ARM, GPU, DSP, WLAN IP subsystems).
  • Complex Block Implementation (Modem, Camera).
  • Full chip, Block level signoff closure (static timing analysis, formal verification, dynamic and leakage power, physical verification, low power).
  • Flow and methodology migration and support.
  • Technology experience on varying process nodes optimized for performance, power ranging from 28nm, 20nm, 16nm, 10nm and 7nm