Roles & Responsibilities
- 7 – 8 years of experience in PnR
- Have done 2-3 Top level PnR with Timing Closure
- Lead a team of Engineers
- Have in-depth knowledge of entire physical design process from RTL to GDS2
generation - which includes floorplan, Placement, CTS, Routing and Sign Off ( STA, PV,
IR/EM) - Have hands-on experience in latest sub-micron technologies below 14nm
- Familiar with Physical Verification flows (DRC/LVS/EM/IR)
- Experience in ECO implementation
- Hands on experience in PnR tools Synopsys ICC II/ Cadence Encounter etc
- Familiarity with any of Scripting languages –PERL, TCL
- Should possess good Leadership Skills
- Must have good communication & problem-solving skills.
- Should be with Go-getter attitude
- Mentor Team Members
- Bachelor/Master Degree in Electronics Engineering
Job Location: Bangalore
Designation: Lead Physical Design Engineer
Qualification: Bachelor/Master’s Degree in Electronic/Electrical Engineering with Major in VLSI/Microelectronics
Number of Positions: 2
Roles & Responsibilities
- 3+ years of experience in AMS/RF layout-design (7nm)
- Good Understanding of CMOS Fundamentals, IC-Fabrication & Circuit-basics
- Good Understanding of Layout-Flow & various Reliability Issues
- Preferred experience in modules like PLL, Data-Converters & PMIC blocks
- Good exposure to EDA tools like Virtuoso LE/XL, Assura, PVS, Calibre
- Preferred experience in Deep Sub-Micron/Finfet / Bi-CMOS technologies
- Independently execute layout-design of the assigned Analog & Mixed-Signal / RF blocks either at Onsite or Off-shore, which includes floor-planning as per area & top-level, parasitic-aware routing & doing various required physical verifications.
- Responsible for the on-time delivery of block-level layouts, with acceptable quality
- Co-ordinate effectively with the customer & team-members, for the successful overall project execution
- Guide junior team-members in their execution of block-level layouts & review their work
- Contribute to effective project-management.
Location: Bangalore
Experience: 3+ Years & Above
Qualification: Bachelor/Master’s Degree in Electronic/Electrical Engineering with Major in VLSI/Microelectronics
Number of Positions: 5
Roles & Responsibilities
- Hands on experience with layouts of important memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array and decoders etc in compiler
context. - Should have worked on 16nm / 14nm / 10nm/ 7nm/ Finfet process technologies .
- Hands on experience with top level memory integration and DRC, LVS, Density verification and cleaning physicals across the compiler space.
- Good handle on IR/EM related issues in memory layouts.
- Must have worked on cadence tools for layout design and Cadence/Mentor/Synopsys tools for physical verification checks.
- Strong knowledge of ultra-deep sub-micron layout design related challenges and good understanding of DFM guidelines.
- Experience & or strong interest in memory compilers developed.
- Excellent and demonstrated team player with ability to work with external customers and in cross functional teams.
Location: Bangalore
Experience: 3+ Years & Above
Qualification: Master’s Degree in Electronic/Electrical Engineering with Major in VLSI/Microelectronics
Number of Positions: 3